Improvements for on-die reflectance arrangements

ABSTRACT

Improved semiconductor reflectance arrangements (e.g., semiconductor devices, systems including semiconductor devices, methods, etc.).

FIELD

The present disclosure relates to improvements for on-die reflectancearrangements (e.g., including semiconductor devices, semiconductorpackages, systems including the same, methods, etc.).

BACKGROUND

There is a drive toward achieving high quality on-die integrationbetween metal oxide semiconductor (MOS) and ones of liquid crystal onsilicon (LCOS), micro-electro mechanical systems (MEMS) and SLM (SpatialLight Modulators) technologies, and there is also a drive towardachieving optical devices using standard MOS technology. Someapplications (e.g., optical applications) of LCOS, MEMS or SLM mayrequire high reflectance areas (e.g., pixel mirrors) to be formed on adie. Improved reflectance arrangements are desired, and further, it isdesirable that improvements be achievable using existing MOS technology,tools and methods, in order to maintain costs within reasonable levels

BRIEF DESCRIPTION OF THE DRAWINGS

A better understanding of the present invention will become apparentfrom the following detailed description of example embodiments and theclaims when read in connection with the accompanying drawings, allforming a part of the disclosure of this invention. While the followingwritten and illustrated disclosure focuses on disclosing exampleembodiments of the invention, it should be clearly understood that thesame is by way of illustration and example only and that the inventionis not limited thereto. The spirit and scope of the present inventionare limited only by the terms of the appended claims.

The following represents brief descriptions of the drawings, wherein:

FIG. 1 illustrates example die, IC and/or electronic system arrangementsthat may incorporate implementations of the present invention;

FIG. 2 shows a close-up cross-sectional view of an example pixel/mirrorarrangement, such view being useful in gaining a more thoroughunderstanding/appreciation of the present invention;

FIGS. 3 and 4 show example plan views of a plurality of pixel mirrorsarranged in an example regular array, such views being useful in gaininga more thorough understanding/appreciation of the present invention;

FIG. 5 represents a magnified cross-sectional view of pixel mirror areasadjacent to an underlying pixel metal interconnection and plug, suchviews being useful in gaining a more thorough understanding/appreciationof the present invention;

FIGS. 6 and 8 illustrate a disadvantageous arrangement for comparisonpurposes with FIGS. 7 and 9 showing an example first embodiment of thepresent invention, with all such FIGS. including magnifiedcross-sectional views of pixel mirror areas adjacent to an underlyingplug;

FIG. 10 shows an example plot of wavelength verses % reflectance fordiffering arrangements, such plot being useful in gaining a morethorough understanding/appreciation of the present invention;

FIG. 11 illustrates a disadvantageous arrangement for comparisonpurposes with FIG. 12 showing an example second embodiment of thepresent invention, with all such FIGS. including magnifiedcross-sectional views of pixel mirror areas adjacent to an underlyingplug;

FIG. 13 illustrates a disadvantageous arrangement for comparisonpurposes with FIG. 14 showing an example third embodiment of the presentinvention, with all such FIGS. including magnified cross-sectional viewsof pixel mirror areas adjacent to an underlying plug;

FIG. 15 illustrates a magnified view of an example disadvantageous pixelhole resultant from the FIG. 13 disadvantageous arrangement, whereasFIG. 16 illustrates a magnified view of an example advantageous pixelhole resultant from the FIG. 14 advantageous arrangement; and

FIG. 17 illustrates a magnified cross-sectional view of pixel mirrorareas adjacent to an underlying pixel metal interconnection and plug ofan advantageous combination embodiment which may includestructures/features of the first, second and third embodiments, withsuch views being useful in gaining a more thoroughunderstanding/appreciation of the present invention.

DETAILED DESCRIPTION

Before beginning a detailed description of the subject invention,mention of the following is in order. When appropriate, like referencenumerals and characters may be used to designate identical,corresponding or similar components in differing FIG. drawings. Further,in the detailed description to follow, example sizes/values/materialsmay be given, although the present invention is not limited to the same.As manufacturing techniques (e.g., photolithography) mature over time,it is expected that devices, apparatus, etc., of smaller size could bemanufactured. Well known power/ground connections to IC devices, ICs andother components may not be shown within the FIGS. for simplicity ofillustration and discussion, and so as not to obscure the invention.Further, arrangements may be shown in simplistic and/or block diagramform in order to avoid obscuring the invention, and also in view of thefact that specifics with respect to implementation are highly dependentupon the platform within which the present invention is to beimplemented, i.e., such specifics should be well within purview of oneskilled in the art. Where specific details (e.g., process flows) are setforth in order to describe example embodiments of the invention, itshould be apparent to one skilled in the art that the invention can bepracticed without, or with variation of, these specific details.

Although example embodiments of the present invention will be describedusing example highly reflective pixel/mirrors that are provided, forexample, for a MOS/LCOS arrangement using MOS technology, practice ofthe invention is not limited thereto. That is, the invention may be ableto be practiced with other types of reflectance arrangements (e.g.,non-pixel mirrors, heat reflectance), and for/with other types oftechnologies (e.g., MEMS, SLM).

FIG. 1 illustrates example die, IC and/or electronic system arrangementsthat may incorporate implementations of the present invention. Moreparticularly, shown is a die or integrated circuit (IC) chip that mayincorporate one or more implementations of the present invention as alower level die or IC chip system. As one example, an implementation ofthe present invention may be highly reflective pixel/mirrors of an LCOSdisplay that is formed on the die or IC. Such die or IC may be part ofan electronic package PAK that incorporates the IC together withsupportive components onto a substrate such as a printed circuit board(PCB) as a packaged system. The packaged system may be mounted, forexample, via a socket SOK onto a system board (e.g., a motherboardsystem). The system board may be part of an overall electronic device(e.g., computer, electronic consumer device, server, communicationequipment) system 100 that may also include one or more of the followingitems: input (e.g., user) buttons B, an output (e.g., display DIS), abus or bus portion BUS, a power supply arrangement PS, and a case CAS(e.g., plastic or metal chassis).

FIG. 2 shows (together with an example dimensional scale) a close-upcross-sectional view 200 of one example pixel/mirror arrangement, suchview being useful in gaining a more thorough understanding/appreciationof the present invention. The example pixel/mirror arrangement may beformed on a substrate that may be topped with a plurality 202 ofinter-layer dielectric (ILD) layers that may include a top ILD layer203, and may have various structures 204 embedded therein. Furtherincluded may be a pixel metal interconnection 220, topped with aninterfacing layer 230 and a via-filled plug 240 (e.g., a tungsten plug).A reflective layer (e.g., aluminum) 250 may be deposited onto thesubstrate and have patterned trenches 210 etched therein so as to formdesired (e.g., substantially square) pixel mirrors 205. Multipleadditional layers 260 (e.g., of SiO2, Si3N4) may be disposed onto thepatterned reflective layer 250 as a reflective enhancement coating (REC)for enhancement, passivation and/or protection of the layer 250. Item280 represents a pixel hole (discussed further ahead), item 295represents an upper plug surface (discussed further ahead) and RLrepresents a reflected light.

FIG. 3 shows an example plan view 300 of a plurality of pixel mirrors205 arranged in an example regular array. It is desired that reflectedlight (RL; FIG. 2) from any single particular pixel mirror 205 besubstantially uniform in reflectance all across an area of that pixelmirror 205. Also, it is desired that reflected light (FIG. 3) besubstantially uniform in reflectance from pixel mirror to pixel mirror205 across the area of the entire array. Any differentials inreflectance within a given pixel mirror or across the array may bedistractive to an end user (e.g., a consumer), and may render any devicehaving the non-uniformity of reflectance both visibly and commerciallyunattractive to consumers.

A pixel hole 280 may represent a distortion that may show up in thereflective layer 250 and/or layers 203, due to distortions(non-planarities) that permeate upwards from an underlying plugstructure. That is, any over-etching of a via fill material (e.g.,tungsten) during an etch-back to achieve plugs within vias, may lead toa disadvantageous plug topography called “plug recess”. That is, anupper plug surface 295 (FIG. 2) may be recessed below a general planelevel of the ILD surface. While traditional MOS technology may not besensitive to such “plug recess” topography, LCOS is. Such recess maypermeate upwards and ultimately showing up as a discontinuity, and thusa change in reflectance, in the reflective layer 250 and/or layers 260.More particularly, thin Aluminum pixels will follow ILD/recessed-plugtopography, to result in the “pixel hole defect”.

In the attempted construction of a die or IC having the aforementionedFIG. 3 pixel mirror array, additional non-uniformities of reflectancewere encountered (beyond pixel hole defects). More particularly, FIG. 4shows an example plan view 400 of a plurality of pixel mirrors arrangedin an example regular array, but with such pixel mirrors and/or arraybeing afflicted by multiple occurrences of non-uniform reflectance. Morespecifically, as to the overall array, a left-hand portion 410 was foundto display a first pattern/level of reflectance, whereas a right-handportion 420 was found to display a second (differing) pattern/level ofreflectance. As to any given pixel, non-uniform reflectance alsooccurred within the boundary of the pixel mirror.

Upon investigation, it was found that various raised ridges and/orlowered valleys (with defined ridgelines 430, 440 therebetween; FIG. 4)had disadvantageously formed in regular patterns into the reflectivelayer 250 and/or layers 260. That is, a first type of ridgeline pattern430 had formed in the right-hand portion 420, whereas a second type ofridgeline pattern 440 had formed in the left-hand portion 410. Furtherinvestigation revealed that the various raised ridges and/or loweredvalleys, as well as the ridgeline patterns 430, 440 representedtopographical artifacts caused by underlying structures/stressespermeating upwards and ultimately showing up in the reflective layer 250and/or layers 260.

For explanation, FIG. 5 (together with an example dimensional scale)represents a magnified cross-sectional view 500 of pixel mirror areasadjacent to the underlying pixel metal interconnection 220 and plug 240.The FIG. 5 description that follows focuses on issues concerning stresslines emanating from underlying pixel metal interconnection 220 andresulting in artifacts (e.g., ridgelines) within upper layers.

During manufacturing, the underlying pixel metal interconnection 220 maybe formed, for example, by deposition of a metal layer, followed by anetching (e.g., dry plasma etching) of the metal layer into desiredinterconnections. Such etched metal interconnections 220 may have asharp topography (e.g., sharp edges). After interconnection 220formation, one or more ILD layers may be deposited (e.g., viatetraethylorthosilicate (TEOS); plasma TEOS (PTEOS), thick TEOS,chemical vapor deposition (CVD), plasma enhanced CVD (PECVD)) fordielectric coverage (entombing) of the etched metal interconnections220.

Through further analysis, it was found that stress lines 510 may emanatefrom ones of the underlying structures (interconnections 220) due to,for example, its prior sharp topography, and may emanate upwards throughthe ILD layers towards the surface thereof. After ILD deposition,chemical mechanical polishing (CMP) may be used to planarize the ILDsurface. Although planarization may be temporarily achieved, suchplanarization does not eliminate the presence of stress lines 510. Thatis, the ILD layer has a residual poly stress structure. It was foundthat such local stress lines 510 may lead to subsequent surfacealteration (non-planarization) of the ILD surface during subsequentproduction steps.

More particularly, after CMP planarization, the ILD may be furtheretched (e.g., via dry etching) to form vertical vias, and then a plugmaterial layer (e.g., tungsten) may be deposited onto the ILD surface tofill the vias. Subsequently, the deposited plug material layer may beetched back from the ILD surface so as to leave plug material onlywithin the vias. It was found that such etch back operation may lead tothe aforementioned surface alteration (non-planarization) of the ILDsurface.

Such happens because of the preexisting non-homogeneous stress withinthe ILD layer. That is, CMP planarizes the ILD surface, but doesn'tchange the stress. As a result, the ILD was found to experiencediffering local etch rates at differing ILD areas having differingstress levels. More particularly, viewing FIG. 5 again, each stress line510 may be viewed as dividing an ILD area into two ILD areas havingdiffering stresses, i.e., an ILD area on a plug-facing-side of thestress line 510, and an ILD area on a non-plug-facing side.

ILD areas on a plug-facing-side of the stress line 510 may have a stresslevel which results in a high local etch rate of these areas, while (incontrast) ILD areas on the other (non-plug-facing) side of the stressline 510 may have a differing stress level which results in a lowerlocal etch rate of these areas. ILD areas experiencing high local etchrates may result in etched valleys in the ILD surface, whereas ILD areasexperiencing low local etch rates may be maintained as raised hills.

Borders between these valleys and hills represent topography steps 580,which may subsequently result in the aforementioned (FIG. 4) ridgelineartifacts 430, 440. As a result, any blanket plasma etching during etchback may destroy ILD planarity (i.e., surface flatness). As on example,an afflicted ILD layer prior to pixel deposition may have topographysteps 580 ranging from tens to hundreds of Angstroms (prior toreflective layer 250 deposition). An overall result is that a non-planarILD surface 520 occurs.

While traditional MOS technology may not be sensitive to suchtopography, LCOS, for example, is. That is, a thin reflective layer(e.g., Al/Cu) 250 deposited onto the non-planar ILD surface will followILD topography, and thus reflectance will vary at differing areas of thelayer 250. For example, FIG. 5 shows (in representative form) a firsttype of reflected light RLA occurring at one area of the pixelarrangement, and a differing type of reflected light RLB occurring at adiffering area of the pixel arrangement. That is, reflective layer 250topography and thus reflected light may contain artifacts fromunderlying structures, for example, metal line structures. In fact, itwas determined that FIG. 4's right-hand ridgeline pattern 430 andleft-hand ridgeline pattern 440 represented differing topographicalartifacts from two differing types of embedded metal line structuresunder the right-hand portion 420 and left-hand portion 410,respectively.

Accordingly, the present invention is directed toward improvements forpreventing reflective layer topography from being affected by underlyingstructures, and further, is directed to improvements for enhancingreflectance of a reflective layer. The present disclosure teaches anumber of differing embodiments which are now discussed as follows underdiffering sub-titles.

Titanium Interfacing Layer:

For explanation, FIG. 6 (together with the indicated dimensional scale)represents a disadvantageous arrangement 600 (for comparison purposeswith FIG. 7) and includes a magnified cross-sectional view of pixelmirror areas adjacent to the underlying plug 240. In formation of areflective layer onto the ILD-layers of the substrate, a reflective(e.g., an Al/Cu pixel) layer 250 (e.g., 145 nm) is deposited, thenpatterned (e.g., via etching), and REC layers 260 are further added forenhancement, passivation and/or protection. In the presentdisadvantageous arrangement, at least three REC layers are added, i.e.,an SiO₂ layer (260-1; e.g., 45 nm), a first Si₃N₄ layer (260-2; e.g., 95nm) and a second Si₃N₄ layer (260-3; e.g., 65 nm), e.g., deposited viaCVD deposition. (Note that a thin long-/short-dash line is used betweenthe layers 260-2 and 260-3, to represent that such were deposited asseparate layers, albeit made of the same material.) Item 280 againrepresents a pixel hole.

FIG. 8 (together with the indicated dimensional scale) shows a furthermagnified cross-sectional view 800 of a portion of FIG. 6, for thepurpose of adding further clarity. With the FIG. 6/8 disadvantageousarrangement, reliability is problematic as such arrangement (althoughnot shown in such magnified views) is afflicted with the aforementionedstress line emanation and reflective layer artifacts.

A left-hand column of the following Table 1 lists the above-discussedexample processing flow for the FIG. 6 disadvantageous arrangement,while a right-hand column lists an example processing flow for anexample first advantageous embodiment. (Bolded text may be used tohighlight some important differences between the two.) TABLE 1Disadvantageous Arrangement Present Embodiment LCOS Processes: LCOSProcesses: Pixel high reflective metal Pixel high reflective metaldeposition. deposition:  Al/Cu   Thin Ti and Al/Cu Pixel patterning.Pixel patterning. REC (Reflective Enhancement REC (ReflectiveEnhancement Coating) - 3 layer stack:: Coating) - 2 layer stack:   SiO₂CVD deposition   SiO₂ CVD deposition   Si₃N₄ CVD deposition   Si₃N₄ CVDdeposition   Si₃N₄ CVD deposition Reliability check - Uniform andReliability check - Non-uniform Enhanced Reflectivity Reflectivity

FIGS. 7 and 9 (together with the indicated dimensional scales) representexample views 700, 900 of an example advantageous embodiment inaccordance with the above Table 1 right-hand processing flow.Unnecessary/redundant discussion of ones of listed processes/featureswhich may be familiar to those skilled in the art, or which may havebeen previously discussed, may be omitted for sake of brevity. That is,the following discussion tends to focus on the differences from thedisadvantageous embodiment, and/or important processes/features of thepresent embodiment.

In formation of a reflective layer onto the ILD-layers of the substrate,a titanium (Ti) interfacing layer 710 (e.g., 45 nm) is first disposedbetween a substrate and upper (e.g., Al/Cu) reflective layer portions.An upper reflective (e.g., an Al/Cu pixel) layer 250 (e.g., 145 nm) isdeposited, then patterned (e.g., via etching). The Ti and Al/Cureflective layer may be deposited using a single process. (Anintervening insulation layer or insulation area (e.g., SiO₂) may also beprovided as an electrical isolator in appropriate areas if electricalisolation is required between any of the conductive Ti or Al/Cu layersand any plug.)

Use of the new Ti and Al/Cu reflective double layer may be accomplishedwith negligible additional cost and existing MOS technology/tools, yetadds significantly improved reliability success. That is, the thin Tilayer was chosen as an under-layer to the Al/Cu layer for improved Al/Cuadhesion to the underlying ILD, and also for improved step coverage,which is critical to reliability. The Ti layer helps lessen/avoid theaforementioned differing stress line etch rates and/or emanation ofartifacts into the subsequent Al/Cu layer, so as to result in a moreuniform pixel and/or array reflectance such as that shown in FIG. 3 (asopposed to FIG. 4).

Again, REC layers 260 may be added for enhancement, passivation and/orprotection. In the present advantageous arrangement, two REC layers (asopposed to three) are added, e.g., a SiO₂ layer (260-1; e.g., 45 nm) anda Si₃N₄ layer (260-2; e.g., 95 nm). These layers may be deposited, forexample, in PECVD (Plasma Enhanced Chemical Vapor Deposition) chambers.

The above-described Ti/REC arrangement may further enhance overallreflectance levels and/or reflectance levels for certain wavelengths.For understanding, FIG. 10 shows an example plot 1000 of wavelengthverses % reflectance. As shown in FIG. 10, Al/Cu is a highly reflectivemetal layer with approximately a 90% reflectance (shown by thediamond-symbol line). In comparison, the triangular-symbol line shows atheoretical % reflectance of a base REC-Al/Cu arrangement, while thesquare-symbol line shows a measured % reflectance of the presentembodiment's (FIGS. 7, 9's) REC-Al/Cu arrangement.

As can be gleaned from the FIG. 10 plot, the present embodiment'sTi/double-stack-REC layers increase the reflectance of the Al/Cu in thewavelength range of 485-745 nm while keeping all reliabilityrequirements. That is, the present embodiment's REC layers improvedpixel reflectance about 1% compared to the theoretical plotted line.

To summarize, the present embodiment's REC layer is unique over thedisadvantageous example (FIGS. 6, 8) in using a Ti interface layer, andin using only double (i.e., double-stacked) versus triple layers (whichrepresents a reduction in manufacturing complexity and cost). With theFIGS. 7/9 advantageous arrangement, reliability and a reflectancelevel/uniformity are improved, and problems concerning theaforementioned stress line emanation and reflective layer artifacts arereduced and/or avoided.

Cap ILD Interfacing Layer:

For explanation, FIG. 11 (together with the indicated dimensional scale)represents a disadvantageous arrangement 1100 (for comparison purposeswith FIG. 12) and includes a magnified cross-sectional view of areasadjacent to the underlying plug 240. Further discussion of FIG. 11substantially parallels the prior FIGS. 5, 6 and 8 discussions, soredundant descriptions are omitted for sake of brevity. With the FIG. 11disadvantageous arrangement, reliability is problematic as sucharrangement is afflicted with the aforementioned stress line emanationand reflective layer artifacts.

A left-hand column of the following Table 2 lists an example processingflow for the FIG. 11 disadvantageous arrangement, while a right-handcolumn lists an example processing flow for another advantageousembodiment. (Bolded text may be used to highlight some importantdifferences between the two.) TABLE 2 Disadvantageous ArrangementPresent Embodiment MOS Processes: MOS Processes: Metal pattern createdby dry Metal pattern created by dry plasma etch. plasma etch. ILD Dep.(PTEOS/Thick TEOS, ILD Dep. (PTEOS/Thin TEOS CVD) CVD) Dry etchedvertical Via. ILD CMP. Tungsten fill of Via. Cap ILD2 Dep. (Thin TEOSWEB (Tungsten Etch Back to CVD) (CMP optional) Via Plug). Dry etchedvertical Via. LCOS Processes: Tungsten fill of Via. Pixel highreflective metal WEB (Tungsten Etch Back to Via deposition. Plug). Pixelpatterning. LCOS Processes: REC (Reflective Enhancement Pixel highreflective metal Coating). deposition. Reflectance check - Non uniformPixel patterning. Reflectivity REC (Reflective Enhancement Coating).Reflectance check - Uniform Reflectivity

FIG. 12 (with the indicated dimensional scale) represents an exampleview 1200 of an example advantageous embodiment in accordance with theabove Table 2 right-hand processing flow. Unnecessary/redundantdiscussion of ones of listed processes which may be familiar to thoseskilled in the art, or which may have been previously discussed, may beomitted for sake of brevity. That is, the following discussion tends tofocus on the differences from the disadvantageous embodiment, and/orimportant processes/features of the present embodiment.

After formation of initial ILD layers (which may have the aforementionedstress lines 510) and before any etching of vertical vias, aplanarization process (e.g., CMP) is applied to planarize a surface ofthe initial ILD layers. Since the CMP process is not selective/sensitivebased upon ILD stress levels, good planarization and thus asubstantially planar surface 1205 may be obtained. Next, a second orinterfacing ILD layer 1210 is deposited (e.g., via thin TEOS CVD) ontothe planarized initial ILD layer surface 1205.

While the planarized initial ILD layer 203′ may still be afflicted withstress lines 510′, the planarity of the such surface 1205 allows suchunderlying stresses not to be passed upwards to the capping or interfaceILD layer 1210. That is, the cap or interface ILD layer 1210 may have asubstantially mono-stressed (or non-stressed, or substantiallyconsistently stressed (within a predetermined limit)) make-up throughoutits body, or at least within an area defining a reflective unit (such asa pixel). The mono-stressed ILD layer 1210 is not afflicted withdiffering etch rates at differing areas thereof during plug etch back,because stress levels are pretty consistent there-through. Accordingly,etch-back of the tungsten fill material (to leave via plugs 240) willleave the mono-stressed ILD layer 1210 with a substantially planarsurface 1220. The result is that stress line artifacts are minimizedand/or eliminated within subsequently formed reflectance and REC layers.

The Implement of a thin Cap ILD layer just before the Via creation stepsmay thus exclude local stress differences, and as a result, provideimproved flatness and uniformity of pixel reflectivity. Such layer maybe summarized as a monostress Cap Inter Layer Dielectric (Cap ILD).Further, since such Cap ILD is formed on top of a planarized base ILD,i.e., is formed after base ILD planarization, the Cap ILD may be furtheror alternately summarized as a post-base-ILD-planarization Cap ILD.

Thus, the Cap ILD interface layer helps lessen/avoid the aforementioneddiffering stress line etch rates and/or emanation of artifacts into thesubsequent Al/Cu layer, so as to result in a more uniform reflectancesuch as that shown in FIG. 3 (as opposed to FIG. 4). Thus, such Cap ILDlayer may add significantly improved reliability success, and may beaccomplished with negligible additional cost and with existing MOStechnology/fools. Further, this embodiment enables high qualityintegration between MOS and LCOS technologies, and enables theproduction of optical devices using standard MOS technology.

Post-Plug-Etch Planarization of ILD:

For explanation, FIG. 13 (with the indicated dimensional scale)represents a disadvantageous arrangement 1300 (for comparison purposeswith FIG. 14) and includes a magnified cross-sectional view of areasadjacent to the underlying plug 240. Further discussion of FIG. 13substantially parallels the prior FIGS. 5, 6 and 8 discussions, soredundant descriptions are omitted for sake of brevity. With the FIG. 13disadvantageous arrangement, reliability is problematic as sucharrangement is afflicted with the aforementioned stress line emanationand reflective layer artifacts.

A left-hand column of the following Table 3 lists an example processingflow for the FIG. 13 disadvantageous arrangement, while a right-handcolumn lists an example processing flow for another advantageousembodiment. (Bolded text may be used to highlight some importantdifferences between the two.) TABLE 3 Disadvantageous ArrangementPresent Embodiment MOS Processes: MOS Processes: Metal pattern createdby dry Metal pattern created by dry plasma etch. plasma etch. ILD Dep.(PTEOS/Thick TEOS, ILD Dep. (PTEOS/Thin TEOS CVD) CVD) ILD CMP. ILD CMP.Dry etched vertical Via. Dry etched vertical Via. Tungsten fill of Via.Tungsten fill of Via. WEB (Tungsten Etch Back to Via WEB (Tungsten EtchBack to Via Plug). Plug). LCOS Processes: LCOS Processes: Pixel highreflective metal Short ILD CMP deposition. Pixel high reflective metalPixel patterning. deposition. REC (Reflective Enhancement Pixelpatterning. Coating). REC (Reflective Enhancement Reflectance check -Non uniform Coating). Reflectivity; 0.5 μm mirror/pixel Reflectancecheck - Uniform plug hole Reflectivity; ˜0.15 μm mirror/pixel plug hole

FIG. 14 (with the indicated dimensional scale) represents an exampleview 1400 of an example advantageous embodiment in accordance with theabove Table 3 right-hand processing flow. Unnecessary/redundantdiscussion of ones of listed processes which may be familiar to thoseskilled in the art, or which may have been previously discussed, may beomitted for sake of brevity. That is, the following discussion tends tofocus on the differences from the disadvantageous embodiment, and/orimportant processes/features of the present embodiment.

After formation of all ILD layers (which may have the aforementionedstress lines 510) and before deposition of any reflective layer 250, ashort (e.g., 30-120 second) planarization process (e.g., CMP) may beapplied to planarize a surface of the ILD layers. Since the CMP processis not selective/sensitive for the ILD portions based upon ILD stresslevels, good planarization is achieveable and a substantially planar ILDsurface 1420 may be obtained.

As mentioned previously, pixel holes 280 may show up in the reflectivelayer 250 and/or layers 203, due to distortions (non-planarities) thatpermeate upwards from underlying plug structure. Although accepted attoday's resolutions, such “pixel hole defects” may become unacceptableand a potential limiter in future high resolution (smaller pixel)displays, as a pixel/hole size ratio may become unacceptable in terms ofthe effect on reflectance. That is, with smaller sized resolutions andpixels, the pixel hole may represent an unacceptable percentage of apixel's overall area. The present post-plug-etch ILD planarization FIG.14 embodiment may also minimize and/or eliminate pixel hole 280distortions.

More particularly, an exposed plug 240 may also be planarized by the CMPprocess, so as to result in a more planarized plug surface 1430 that maybe substantially planar to the ILD planar surface 1420. Since thesurfaces 1420, 1430 are rendered substantially planar (with minimal orno plug-recess, there are no or only minimal plug distortions(non-planarities) that may permeate upwards to show up in the reflectivelayer 250 and/or layers 203.

FIG. 15 shows a magnified view 1500 of an example pixel hole 280 thatmay be resultant from the FIG. 13 disadvantageous arrangement, whereasFIG. 16 shows a magnified view 1600 of a significantly reduced examplepixel hole 280′ that may be resultant form the present post-plug-etchILD planarization FIG. 14 embodiment. Those skilled in the art willrecognize that the greater the degree of coincidence between theplanarized plug surface 1430 and planarized ILD surface 1420, the morethe pixel hole 280′ will be reduced (or even eliminated).

Thus, post-plug-etch ILD planarization may help lessen/avoid emanationof stress-line and/or pixel recess artifacts into the subsequent Al/Culayer, so as to result in a more uniform reflectance such as that shownin FIG. 3 (as opposed to FIG. 4). Thus, post-plug-etch ILD planarizationmay add significantly improved reliability success, and may beaccomplished with negligible additional cost and with existing MOStechnology, tools, methods. Further, this embodiment enables highquality integration between MOS and LCOS technologies, and enables theproduction of optical devices using standard MOS technology. Onealternative name for the present embodiment may be an ILD CMP postTungsten Etch Back (WEB) embodiment.

CONCLUSION

In beginning to conclude, reference in the specification to “oneembodiment”, “an embodiment”, “example embodiment”, etc., means that aparticular feature, structure, or characteristic described in connectionwith the embodiment is included in at least one embodiment of theinvention. The appearances of such phrases in various places in thespecification are not necessarily all referring to the same embodiment.Further, when a particular feature, structure, or characteristic isdescribed in connection with any embodiment or component, it issubmitted that it is within the purview of one skilled in the art toeffect such feature, structure, or characteristic in connection withother ones of the embodiments and/or components.

For example, FIG. 17 illustrates an example embodiment that combines allof the aforementioned embodiments. More particularly, such embodimentincludes an entombed ILD layer 203′ (which may have stress lines 510′)having a substantially (CMP) planarized upper ILD surface 1205, a secondor interfacing (mono-stress) ILD layer 1210 having a substantially (CMP)planarized upper ILD surface 1420 and substantially (CMP) planarizedplug surface 1430, and finally, a titanium (Ti) interfacing layer 710disposed between a substrate and upper (e.g., Al/Cu) reflective layerportions 250. Redundant discussion of other ones of the FIG. 17components that may have been previously discussed, are omitted for sakeof brevity.

For ease of understanding, certain ones of the above method proceduresmay have been delineated as separate procedures; however, theseseparately delineated procedures should not be construed as necessarilyorder dependent in their performance, i.e., some procedures may be ableto be performed in an alternative ordering, simultaneously, etc.

This concludes the description of the example embodiments. Although thepresent invention has been described with reference to a number ofillustrative embodiments thereof, it should be understood that numerousother modifications and embodiments can be devised by those skilled inthe art that will fall within the spirit and scope of the principles ofthis invention. More particularly, reasonable variations andmodifications are possible in the component parts and/or arrangements ofthe subject combination arrangement within the scope of the foregoingdisclosure, the drawings and the appended claims without departing fromthe spirit of the invention. In addition to variations and modificationsin the component parts and/or arrangements, alternative uses will alsobe apparent to those skilled in the art.

1. A semiconductor device comprising: a light reflective unit includingat least one of: a titanium interface layer disposed between a substrateand reflective layer portions; an interface inter-layer dielectric (ILD)layer disposed between a planarized ILD and a reflective layer; and, apost-plug-etch planarized ILD disposed between a substrate and areflective layer.
 2. A semiconductor device as claimed in claim 1,comprising the light reflective unit including the titanium interfacelayer disposed between the substrate and reflective layer portions.
 3. Asemiconductor device as claimed in claim 2, comprising a reflectiveenhancement coating (REC) of less than three stacked deposition layerson the reflective layer portions.
 4. A semiconductor device as claimedin claim 2, where the reflective layer portions include at least one ofaluminum, copper, silver and gold material.
 5. A semiconductor device asclaimed in claim 1, comprising the light reflective unit including theinterface ILD layer disposed between the planarized ILD and thereflective layer.
 6. A semiconductor device as claimed in claim 5, wherethe interface ILD layer is one of a non-stressed, mono-stressed andsubstantially consistently stressed interface ILD layer.
 7. Asemiconductor device as claimed in claim 5, where the interface ILDlayer is one of a tetraethylorthosilicate (TEOS); plasma TEOS (PTEOS),thick TEOS, chemical vapor deposition (CVD) and a plasma enhanced CVD(PECVD) deposited interface ILD layer.
 8. A semiconductor device asclaimed in claim 5, where the planarized ILD is one of a mechanicallyand a chemical mechanical polish (CMP) planarized ILD.
 9. Asemiconductor device as claimed in claim 1, comprising the lightreflective unit including the post-plug-etch planarized ILD disposedbetween the substrate and the reflective layer.
 10. A semiconductordevice as claimed in claim 9, where the post-plug-etch planarized ILD isone of a mechanically and a chemical mechanical polish (CMP)post-plug-etch planarized ILD.
 11. A semiconductor device as claimed inclaim 9, comprising at least one post-plug-etch planarized plug in thepost-plug-etch planarized ILD, with major planarized surfaces of the atleast one post-plug-etch planarized plug and the post-plug-etchplanarized ILD being substantially co-planar with one another.
 12. Asystem comprising: at least one item selected from a list of: anelectronic package, PCB, socket, bus portion, input device, outputdevice, power supply arrangement and case; and a semiconductor deviceincluding: a light reflective unit including at least one of: a titaniuminterface layer disposed between a substrate and reflective layerportions; an interface inter-layer dielectric (ILD) layer disposedbetween a planarized ILD and a reflective layer; and, a post-plug-etchplanarized ILD disposed between a substrate and a reflective layer. 13.A system as claimed in claim 12, comprising the light reflective unitincluding the titanium interface layer disposed between the substrateand reflective layer portions.
 14. A system as claimed in claim 13,comprising a reflective enhancement coating (REC) of less than threestacked deposition layers on the reflective layer portions.
 15. A systemas claimed in claim 13, where the reflective layer portions include atleast one of aluminum, copper, silver and gold material.
 16. A system asclaimed in claim 12, comprising the light reflective unit including theinterface ILD layer disposed between the planarized ILD and thereflective layer.
 17. A system as claimed in claim 16, where theinterface ILD layer is one of a non-stressed, mono-stressed andsubstantially consistently stressed interface ILD layer.
 18. A system asclaimed in claim 16, where the interface ILD layer is one of atetraethylorthosilicate (TEOS); plasma TEOS (PTEOS), thick TEOS,chemical vapor deposition (CVD) and a plasma, enhanced CVD (PECVD)deposited interface ILD layer.
 19. A system as claimed in claim 16,where the planarized ILD is one of a mechanically and a chemicalmechanical polish (CMP) planarized ILD.
 20. A system as claimed in claim12, comprising the light reflective unit including the post-plug-etchplanarized ILD disposed between the substrate and the reflective layer.21. A system as claimed in claim 20, where the post-plug-etch planarizedILD is one of a mechanically and a chemical mechanical polish (CMP)post-plug-etch planarized ILD.
 22. A system as claimed in claim 20,comprising at least one post-plug-etch planarized plug in thepost-plug-etch planarized ILD, with major planarized surfaces of the atleast one post-plug-etch planarized plug and the post-plug-etchplanarized ILD being substantially co-planar with one another.
 23. Amethod of forming a semiconductor device including a light reflectiveunit, the method comprising at least one of: disposing a titaniuminterface layer between a substrate and reflective layer portions of thelight reflective unit; planarizing a base inter-layer dielectric (ILD)layer, and then depositing an interface ILD layer thereon beforedepositing a reflective layer of the light reflective unit; and,applying planarization to a plug-etched ILD to obtain a post-plug-etchplanarized ILD, before depositing a reflective layer of the lightreflective unit.
 24. A method as claimed in claim 23, comprising thedisposing of the titanium interface layer between the substrate andreflective layer portions of the light reflective unit.
 25. A method asclaimed in claim 24, comprising depositing a reflective enhancementcoating (REC) of less than three stacked deposition layers on thereflective layer portions.
 26. A method as claimed in claim 24, wherethe reflective layer portions include at least one of aluminum, copper,silver and gold material.
 27. A method as claimed in claim 23,comprising the planarizing of the base inter-layer dielectric (ILD)layer, and then depositing the interface ILD layer thereon beforedepositing the reflective layer of the light reflective unit.
 28. Amethod as claimed in claim 27, where the interface ILD layer is one of anon-stressed, mono-stressed and substantially consistently stressedinterface ILD layer.
 29. A method as claimed in claim 27, where theinterface ILD layer is deposited using at least one of atetraethylorthosilicate (TEOS); plasma TEOS (PTEOS), thick TEOS,chemical vapor deposition (CVD) and a plasma enhanced CVD (PECVD)deposition.
 30. A method as claimed in claim 27, where the planarizingis performed using at least one of a mechanical and a chemicalmechanical polish (CMP) planarization.
 31. A method as claimed in claim23, comprising applying the planarization to the plug-etched ILD toobtain the post-plug-etch planarized ILD, before depositing thereflective layer of the light reflective unit.
 32. A method as claimedin claim 31, where the planarization is performed using at least one ofa mechanical and a chemical mechanical polish (CMP) planarization.
 33. Amethod as claimed in claim 31, comprising planarizing to obtain at leastone post-plug-etch planarized plug in the post-plug-etch planarized ILD,so as to have major planarized surfaces of the at least onepost-plug-etch planarized plug and the post-plug-etch planarized ILD besubstantially co-planar with one another.